Flash memory is a type of electronic memory media that can be rewritten and that can hold its content without the consumption of power. Flash memory devices generally have life spans from 100K to 300K write cycles. Unlike dynamic random access memory (DRAM) devices and static random memory (SRAM) devices in which a single byte can be erased, flash memory devices are typically erased and written in fixed multi-bit blocks or sectors. Flash memory technology evolved from electrically erasable read only memory (EEPROM) chip technology, which can be erased in situ. Flash memory devices are less expensive and denser, meaning that flash memory devices can hold more data per unit area. This new category of EEPROMs has emerged as an important non-volatile memory that combines the advantages of erasable programmable read only memory (EPROM) density with EEPROM electrical erasability.
Conventional flash memory devices are constructed in a cell structure wherein a single bit of information is stored in each cell. FIG. 1 is a cross section view of an exemplary flash memory device. Memory device 100 comprises a metal oxide (MOS) transistor structure having a source 101, a drain 102, and a channel area 103 in a substrate 110, as well as having a stacked gate structure 104 overlying the channel 103. The stacked gate 104 may further include a thin gate dielectric layer 105 (sometimes referred to as a layer of tunnel oxide) formed on the surface of substrate 110. Stacked gate 104 also includes a polysilicon floating gate 106 overlying tunnel oxide 105 and an interpoly dielectric layer 107 overlying floating gate 106. Interpoly dielectric 107 is often a multilayer insulator such as an oxide-nitride-oxide (ONO) layer having two oxide layers sandwiching a nitride layer. Lastly, a polysilicon control gate 108 overlies interpoly dielectric layer 107.
Control gate 108 is coupled with a row of such cells by a common wordline in a typical NOR configuration. In addition, the drain regions 102 of a column of cells are coupled together by a common bitline. When a voltage is applied to control gate 108, an electric field is formed in channel 103 and current can be conducted between source 101 and drain 102. Typically, the source 101 of each cell is coupled to a common source terminal. In operation, individual flash cells are addressed via the respective bitline and wordline using peripheral decoder and control circuitry for programming (writing) reading and erasing the cell.
The single bit stacked gate flash memory cell is typically programmed by “channel hot electron injection” in which a high positive voltage is applied to control gate 108, source 101 is coupled to ground and drain 102 is coupled to a positive voltage. The resulting high electric field across the channel region accelerates electrons toward the drain region and imparts enough energy for them to become hot electrons. The hot electrons are scattered (e.g., by impurities or the substrate lattice structure of the substrate in the channel region) and are redirected toward the floating gate by the vertical field established by the positive control gate voltage. If the electrons have enough energy, they can tunnel through gate oxide 105 into floating gate 106 and become trapped there. This changes the threshold voltage VT, and thereby the channel conductance, of cell 100.
In order to erase a typical single bit stacked gate flash memory cell, a voltage (e.g., 10 to 12 volts) is applied to source 101, control gate 108 is held at a negative potential, and drain 102 is allowed to float. Under these conditions, an electrical field is developed across tunnel oxide 105 between floating gate 106 and source 101. The electrons that are trapped in floating gate 106 flow toward and cluster at the portion of floating gate 106 overlying source region 101. The electrons are then extracted from floating gate 106 and into source region 101 by way of Fowler-Nordheim tunneling through tunnel oxide 105. Cell 100 is erased as the electrons are removed from floating gate 106.
More recently, nitride read only memory (NROM) devices (also known as dual bit flash memory) have been introduced that allow the storage of two bits of information in two separate cells of a single memory device. The NROM device uses what is known as a virtual ground architecture in which the source of one cell in the device serves as the drain of the other cell. FIG. 2 illustrates an exemplary prior art nitride read only memory device 200. Memory device 200 comprises a silicon nitride layer 201 which is disposed between a top silicon dioxide layer 202 and a bottom silicon dioxide layer 203, forming an ONO layer 204. A polysilicon layer 205 resides over the ONO layer 204 and acts as a wordline for memory device 200. A first bitline 206 and a second bitline 207 run underneath the ONO layer 204. Memory device 200 resides on P-type substrate 208 with the conductive portion of the bitlines 206 and 207 formed from an N+ implant, such that a channel 209 is formed across the P-type substrate 208 when the bitlines are biased. Memory device 200 is a single transistor having interchangeable source and drain components formed from bitlines 206 and 207 with a gate formed as part of a polysilicon wordline 205.
Silicon nitride layer 201 forms a charge trapping layer. Programming a cell is accomplished by applying appropriate voltages to one of the bitlines which acts as the drain terminal, to the gate (e.g., polysilicon layer 205) and grounding the bitline acting as the source terminal. The voltages generate electrical fields along channel 209 causing electrons to accelerate and jump from substrate layer 208 into silicon nitride layer 201, which is known as hot electron injection. Since the electrons gain the most energy at the drain, these electrons become trapped and remain stored in silicon nitride layer 201 near the ONO/bitline junction. Since the silicon nitride layer 201 is non-conducting, a first charge can be injected into silicon nitride layer 201 near the junction of bitline 206 and ONO layer 204 and stored as left bit 210. Similarly, and a second charge can be injected and stored separately from the first charge in silicon nitride layer 201 near the junction of bitline 207 and ONO layer 204 and stored as right bit 211.
Nitride read only memory device 200 is symmetrical allowing the drain and the source to be interchangeable. Thus, bitline 206 may serve as the drain terminal and bitline 207 may serve as the source terminal when programming left bit 210. Likewise, bitline 207 may serve as the drain terminal and bitline 206 may serve as the source terminal for programming right bit 211.
Erasing nitride read only memory device 200 involves a tunneling enhanced hot hole (TEHH) injection process in which holes are injected into the region of nitride layer where a charge is stored. For example, a negative high voltage is applied to the control gate (e.g., polysilicon layer 205) and a positive high voltage is applied to one or both of the bitlines 206 and 207 which results in holes entering nitride layer 201 where recombination with the stored electrons occurs. However, hot hole injection can cause degradation of oxide layer 203, particularly in the area of the junction of ONO layer 204 and bitlines 206 and 207 after repeated program/erase cycles.
Additionally, it is difficult to control exactly where in nitride layer 201 the electrons and holes are injected. Typically, the electrons of a stored bit (e.g., left bit 210) are believed to be concentrated along the edge of the bitline/ONO junction because the electrons gain the most energy at the drain (e.g., bitline 206 of FIG. 2). However, it is not clearly understood where the greatest concentration of holes occurs when they are injected into nitride layer 201. Ideally, the concentration profiles should overlap identically to maximize the recombination of electrons and holes in the nitride layer. In reality, the charges do no overlap identically and residual charges of electrons build up in the region of nitride layer 101 between left bit 210 and right bit 211.
FIG. 3 shows an exemplary distribution of electrons and holes in a prior art nitride read only memory device. Electron distribution 301 shows the concentration profile of electrons within nitride layer 201. Hole distribution 302 shows the concentration profile of holes within nitride layer 201. As shown in FIG. 3, the distribution of electrons is concentrated in the vicinity of the bitline/ONO junction (e.g., left bit 210). However, the concentration profile of hole distribution 302 does not overlap the concentration profile of electron distribution 301. This results in an area 303 within the channel region of nitride layer 201 with a greater concentration profile of holes and a second are 304 with a greater concentration profile of electrons. The net result therefore, is a build up of residual charges within the channel region.
Thus, prior art methods for erasing a nitride read only memory device fail to effectively remove charges from the channel region of the nitride layer. Additionally, prior art methods for erasing a nitride read only memory device (e.g., tunneling enhanced hot hole injection) can cause physical degradation of the oxide layer of the memory device.